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description the A4407 is an automotive power management ic that uses a 2.2 mhz constant on-time (cot) buck pre-regulator to supply a 5 v linear regulator, a 5 v tracking/protected linear regulator, a 3.3 v linear fet controller/driver, and a 1.2 v/1.5 v/1.8 v linear fet controller/driver. the A4407 provides a pin to set the master reference for the 5 v tracking regulator to either the 3.3 v or the 5 v output. the on-time of the buck is internally adjusted as a function of v in to maintain the 2.2 mhz switching frequency. efficient operation is achieved by using the buck pre-regulator to drop the input voltage before supplying the linear regulators. designed to supply can and microprocessor power supplies in high temperature environments, the A4407 is ideal for under hood applications. the switching regulator is designed to operate at a nominal switching frequency of 2.2 mhz. the high switching frequency enables the customer to select low value inductors and ceramic capacitors while avoiding emi in the am frequency band. protection features include: undervoltage lockout, pulse-by- pulse current limit, lx short circuit protection, and thermal shutdown. in case of a shorted load all linear regulators feature foldback overcurrent protection. in addition, the v5p output is protected from a short-to-battery event. the A4407 features both a logic level and a high-voltage (current and voltage limited) enable input. the A4407 also features a power-on-reset (npor) output with adjustable delay for microprocessor control. the A4407 is supplied in a low profile (1.1 mm) 24-lead tssop package with exposed pad for enhanced thermal dissipation (suffix lp). the package is lead (pb) free with 100% matte-tin leadframe plating. A4407-ds, rev. 2 features and benefits ? aec q100 grade 0 qualified ? internal buck pre-regulator followed by ldo outputs ? 5.5 to 36 v v in operating range (50 v maximum); for start/stop, cold crank, and load dump requirements ? constant on-time (cot) buck pre-regulator ? valley current sensing achieves shortest buck on-times ? 2.2 mhz (v in - adjusted) switching frequency ? 5 v internal low-dropout tracking linear regulator with foldback short circuit and short-to-battery protections ? 5 v internal low-dropout linear regulator with foldback short circuit protection ? 3.3 v external fet controller/driver with programmable current limit and foldback short circuit protection ? 1.2 v/1.5 v/1.8 v external fet controller/driver with programmable current limit and foldback protection ? power-on reset (npor) with adjustable rising delay ? logic enable input (enb) for microprocessor control ? ignition enable input (enbat) for remote startup ? ignition status indicator (enbats) output ? buck pulse-by-pulse overcurrent protection ? buck lx short circuit protection (latched) ? missing asynchronous diode protection (latched) ? uvlo for vin, charge pump, and the internal rail ? thermal shutdown protection ? ? 40oc to 150oc junction temperature range 2.2 mhz constant on-time buck regulator with two external and two internal linear regulators package: 24-pin tssop with exposed thermal pad (suffix lp) simplified functional block diagram not to scale A4407 applications: automotive control modules, such as: ? electronic power steering (eps) ? transmission control (tcu) ? antilock braking (abs) ? emissions control external controller with foldback (1v2) charge pump A4407 5. 45 v (vreg) pwm control (v5) 5 v ldo with foldback thermal shutdown (tsd) soft start 5 v ldo (v5p) with tracking, foldback, and short to v bat protection npor output tracking control 2:1 mux 3v3 v5 (3v3) external controller with foldback
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating unit vin pin ? 0.3 to 50 v lx pin v lx ?0.3 to 50 v t < 250 ns ?1.5 v vcp, cp1, cp2 pins ? 0.3 to 60 v isen ? pin ? 0.5 to 1 v isen + pin ? 0.5 to 0.5 v enbat pin the enbat pin is internally clamped to approximately 8.5 v due to an esd protection device. ? 0.3 v ? 50 to 50 ma vreg pin ? 0.3 to 8 v g1v2 and g3v3 pins these pins are internally clamped by an esd protection device. clamp voltages range from 10 v (min) to 15 v (max). ? 0.3 v cl1v2 and cl3v3 pins ? 0.3 to 10 v v5p pin ?0.3 to v in +0.5 v v5 pin ? 0.3 to 7 v ton pin ? 0.3 to 50 v npor, cpor, enb, enbats, track, 1v2, and 3v3 pins ? 0.3 to 7 v operating ambient temperature t a range k ? 40 to 135 oc junction temperature t j ? 40 to 150 oc storage temperature range t stg ? 40 to 150 oc *absolute maximum ratings are limiting values that should not be exceeded under worst case operating conditions or damage may o ccur. stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings onl y, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is not implied. exposure to absolute-maximum?rated conditions for extended periods may affect device reliability. selection guide part number operating ambient temperature range t a , (c) package packing* leadframe plating A4407klptr-t ?40 to 135 24-pin tssop with exposed thermal pad 4000 pieces per 13-in. reel 100% matte tin *contact allegro ? for additional packing options. thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja on 4-layer pcb based on jedec standard 28 oc/w *additional thermal information available on the allegro ? website.
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram vin ton cp2 cp1 vcp f 0.1 f f c in1 c in2 f f f f f i sense i sense f k k k 8.5 v microcontroller 5 v protected enable k r ton h (max) f c out1 soft start ic power control foldback foldback external controller with foldback external controller with foldback fault logic and timing tracking c out2 r sense d buck d in f f f f f v out3v3 q 3v3 q 1v2 c outv5 c outv5p c out3v3 c out1v2 v out1v2 f f k k k k v microcontroller reset v outv5 v outv5p v ign d1 b240a a . vin(pin2) d2 b240a protec ? on diodes d1 and d2 are required when the v5p pin is driving a wiring harness (or excessively long pcb trace) where parasi ? c inductance will cause the voltage at the v5p to momentarily transi ? on above vin or below ground during a fault condi ? on. a
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 cp2 cp1 lx isen+ isen ? vreg cl3v3 g3v3 3v3 cl1v2 g1v2 1v2 vcp vin gnd ton enbat enb enbats npor cpor track v5 v5p pad terminal list table number name function 1 vcp charge pump reservoir capacitor 2 vin input voltage 3 gnd ground 4 ton buck regulator on-time programming pin 5 enbat ignition enable input from the key/switch via a 1 k resistor 6 enb logic enable input from the microcontroller 7 enbats open drain ignition status output 8 npor open-drain fault indication output; active low 9 cpor npor delay programming pin 10 track sets the v5p tracking to either the 3v3 or v5 linear regulator 11 v5 5 v regulator output 12 v5p 5 v tracking/protected regulator output 13 1v2 1.2 v/1.5 v/1.8 v regulator output 14 g1v2 gate driver to the external mosfet for 1.2 v/1.5 v/1.8 v regulation 15 cl1v2 1.2 v/1.5 v/1.8 v current sense/limit input 16 3v3 3.3 v regulator output 17 g3v3 gate driver to the external mosfet for 3.3 v regulation 18 cl3v3 3.3 v current sense/limit input 19 vreg buck regulator dc output and input to the 3.3 v external regulator 20 isen ? buck negative current sense pin, sense resistor and diode node 21 isen + buck positive current sense pin, sense resistor/ground node 22 lx buck regulator switching node 23 cp1 charge pump capacitor connection 24 cp2 charge pump capacitor connection ? pad exposed thermal pad for enhanced heat dissipation
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com general specifications functional input voltage v in(func) A4407 functional, parameters not guaranteed 5.5 ? 46 v operating input voltage v in(op) 5.5 13.5 36 v supply quiescent current 1 i q v in = 13.5 v, v ign > v ign(h) or v enb > v enb(h) , no load on vreg ?10?ma i q(sleep) v in = 13.5 v, v ign < v ign(l) and v enb < v enb(l) , no load on vreg ??10 a buck switching regulator (vreg) switcher output ? regulating v reg(pwm) v in(swnom) < v in < 27 v, v enb = high, 100 ma < i vreg < 1100 ma 5.30 5.45 5.60 v switcher output ? dropout v reg(100%) v in = 5.5 v, lx at 100% duty cycle, i vreg = 1100 ma 5.03 ? ? v v in = 6.4 v and lx at 100% duty cycle, i vreg = 200 ma ? ? 6.38 v switcher period 2 t sw(l) v in(swl) < v in < v in(swnom) , r ton = 412 k ? 1.6 ? s t sw(nom) v in(swnom) < v in < v in(swh) , r ton = 412 k ? 450 ? ns t sw(h) v in(swh) < v in < 36 v, r ton = 412 k ? 1.6 ? s switcher on-time t on v in = 7.5 v, r ton = 412 k 1030 1290 1550 ns v in = 13.5 v, r ton = 412 k 160 200 240 ns v in = 27 v, r ton = 412 k 80 118 135 ns v in = 35 v, r ton = 412 k 225 280 335 ns switcher period threshold v in(swl) v in falling, t sw changes from t sw(l) to 100% duty cycle 6.2 6.5 6.8 v v in(swnom) v in falling, t sw changes from t sw(nom) to t sw(l) 8.0 8.6 9.2 v v in(swh) v in rising, t sw changes from t sw(nom) to t sw(h) 28 31 34 v switcher period hysteresis v in(swl)hys relative to the vin voltage that initially caused the switcher period to change ? 250 ? mv v in(swnom) hys relative to the vin voltage that initially caused the switcher period to change ? 250 ? mv v in(swh)hys relative to the vin voltage that initially caused the switcher period to change ? 700 ? mv switch on-resistance r ds(on) t j = 25c, i ds = 0.1 a ? 135 180 m t j = 150c, i ds = 0.1 a ? 270 360 m minimum on-time t on(min) v in = 13.5 v, r ton = 49.9 k ?6590ns minimum off-time t off(min) v in = 13.5 v 85 110 140 ns electrical characteristics valid at 5.5 v < v in < 36 v, ? 40oc < t j < 150oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at 5.5 v < v in < 36 v, ? 40oc < t j < 150oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit buck switching regulator (vreg) (continued) current feedback gain 2 g isen ? 4.0 ? v/v error amplifier transconductance 2 g m ? 7.5 ? a/v error amplifier open loop gain 2 av ol ?57?db 0 db crossover frequency 2 f c v in = 13.5 v, r sense = 300 m , c o = 10 f, r l = 5.5 ? 65 ? khz soft start ramp time t ss ?10?ms 5 v and 5vp linear regulators v5 accuracy and load regulation err v5 10 ma < i v5 < 215 ma, v reg 5.25 v 4.9 5.0 5.1 v v5p accuracy and load regulation err v5p 10 ma < i v5p < 280 ma, v reg 5.25 v 4.9 5.0 5.1 v v5p/3v3 tracking ratio v v5p / v 3v3 1.507 1.515 1.523 ? v5p/3v3 tracking accuracy err track3v3 2.69 v < v 3v3 < 3.37 v, i v5p = 75 ma, 5.5 v < v in < 27 v ? 0.5 ? +0.5 % v5p/v5 tracking accuracy 3 err trackv5 i v5p = i v5 = 75 ma, 5.5 v < v in < 27 v, ?20c < t j < 150c ? 25 ? +25 mv i v5p = i v5 = 75 ma, 5.5 v < v in < 27 v, t j = ?40c ? 32 ? +32 mv 3.3 v linear regulator and fet driver 3v3 accuracy err 3v3 10 ma < i 3v3 < 700 ma 3.23 3.30 3.37 v 3v3 input resistance r in3v3 ? 300 ? k g3v3 source current 1 i g3v3(src) v 3v3 = 3.0 v, v g3v3 = v g3v3(max) ? 1 v ? 160 ? 320 ?480 a g3v3 sink current 1 i g3v3(sink) v 3v3 = 3.6 v, v g3v3 = 6 v 0.5 4 ? ma g3v3 maximum voltage v g3v3(max) v 3v3 = 3.0 v 9 ? 15 v g3v3 minimum voltage v g3v3(min) v 3v3 = 3.6 v ? 0.7 1.0 v g3v3 output impedance 2 r out(g3v3) ? 175 ? 3v3 external fet gate capacitance 2 c iss3v3 250 ? 5200 pf 1.2 v/1.5 v/1.8 v linear regulator and fet driver 1v2 accuracy err 1v2 10 ma < i 1v2 < 500 ma 1.174 1.205 1.236 v 1v2 bias current 1 i 1v2 ? ? 100 ? na g1v2 source current 1 i g1v2(src) v 1v2 = 0.9 v, v g1v2 = v g1v2(max) ? 1v ? 120 ? 240 ?360 a g1v2 sink current 1 i g1v2(sink) v 1v2 = 1.5 v, v g1v2 = 6 v 0.5 3 ? ma g1v2 maximum voltage v g1v2(max) v 1v2 = 0.9 v 9 ? 15 v g1v2 minimum voltage v g1v2(min) v 1v2 = 1.5 v ? 0.7 1.0 v g1v2 output impedance 2 r out(g1v2) ? 175 ? 1v2 external fet gate capacitance 2 c iss1v2 250 ? 3900 pf charge pump (vcp) vcp output voltage v cp v cp ? v in 4.1 6.6 ? v vcp switching frequency f sw(cp) ? 100 ? khz continued on the next page?
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at 5.5 v < v in < 36 v, ? 40oc < t j < 150oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page? logic enable input (enb) enb logic input threshold v enb(h) v enb rising ? ? 2.0 v v enb(l) v enb falling 0.8 ? ? v enb logic input current 1 i enb(in) v enb = 3.3 v ? ? 100 a enb pulldown resistance r enb ?60?k ignition enable input (enbat) and ignition status output (enbats) enbat and enbats thresholds v ign(h) v ign rising via a 1 k series resistance, measure v ign when iq occurs ? 3.3 4.0 v v ign(l) v ign falling via a 1 k series resistance, measure v ign when i q(sleep) occurs 2.2 2.7 ? v enbat input current 1 i enbat(in) v ign = 5.5 v via a 1 k series resistance ? 50 100 a v ign = 0.8 v via a 1 k series resistance 0.5 ? 5 a enbat input resistance r enbat ? 650 ? k enbats output voltage v enbats(l) i enbats = 4 ma ? ? 400 mv enbats leakage current 1 i enbats(lkg) v enbats = 3.3 v ? ? 1 a enbats turn-on delay t enbats sleep mode to v enbats = 3.3 v ? 11 ? ms track input track voltage threshold v track(h) v track rising ? ? 2.0 v v track(l) v track falling 0.8 ? ? v track bias current 1 i track(bias) ? ? 100 ? a npor output npor power-up delay t npor c por = 0.22 f ? 20 ? ms npor output voltage v npor(l) v enb = high or v enbat = high, v reg < v reguv(l) or v 3v3 < v 3v3uv(l) , i npor 4ma ? ? 400 mv v enbat = low, v enb transitioning low, v reg = 5.45 v, i npor 0.3 ma, 0.8 v < v 3v3 < err 3v3 , 0c t j 150c ? 350 800 mv v enbat = low, v enb transitioning low, v reg = 5.45 v, i npor 0.3 ma, 1.0 v < v 3v3 < err 3v3 , ? 40c t j 150c ? ? 800 mv npor leakage current 1 i npor(leak) v npor = 3.3 v ? ? 1 a cpor characteristics cpor charge current 1 i cpor(src) ? ? 13 ? a cpor voltage threshold v cpor(h) v cpor rising 1.0 1.2 1.4 v
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at 5.5 v < v in < 36 v, ? 40oc < t j < 150oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit npor thresholds vreg uvlo thresholds v reguv(h) v reg rising, npor transitions high 4.80 5.00 5.20 v v reguv(l) v reg falling, npor transitions low 4.75 4.94 5.14 v vreg uvlo hysteresis v reguvhys ?60?mv 3v3 uvlo thresholds v 3v3uv(h) v 3v3 rising, npor transitions high 2.80 2.95 3.10 v v 3v3uv(l) v 3v3 falling, npor transitions low ? 2.83 ? v 3v3 uvlo hysteresis v 3v3uvhys ? 125 ? mv 1v2 uvlo thresholds v 1v2uv(h) measured as percentage of err 1v2 ; v 1v2 rising, npor transitions high 85 89 93 % v 1v2uv(l) measured as percentage of err 1v2 ; v 1v2 falling, npor transitions low ?84? % 1v2 uvlo hysteresis v 1v2uvhys ?5?% buck (vreg) current protection vreg isen voltage threshold v isen(th) v isen+ ? v isen? 265 350 435 mv vreg valley current limit i lim(valley) r sense = 300 m , v in > v insw(l) 883 1167 1450 ma vreg peak current limit i lim(peak) 3.0 5.5 ? a 3.3 v overcurrent protection 3v3 overcurrent threshold v cl3v3 v reg ? v cl3v3 210 235 280 mv 3v3 current limit i 3v3lim r cl3v3 = 300 m 700 783 ? ma 3v3 foldback threshold i 3v3fb v 3v3 = 0 v, v reg ? v cl3v3 48 65 90 mv 1.2 v/1.5 v/1.8 v overcurrent protection 1v2 overcurrent threshold v cl1v2 v 1v2 = 1.2 v, v 3v3 ? v cl1v2 179 218 245 mv 1v2 current limit i 1v2lim r cl1v2 = 390 m 459 559 ? ma 1v2 foldback threshold i 1v2fb v 1v2 = 0 v, v 3v3 ? v cl1v2 45 60 84 mv 5vp overcurrent protection v5p current limit 1 i v5plim v v5p = 5 v ? 280 ? 415 ? ma v5p foldback current 1 i v5pfb v v5p = 0 v ? 70 ? 110 ? 150 ma 5v overcurrent protection v5 current limit 1 i v5lim v v5 = 5 v ? 215 ? 310 ? ma v5 foldback current 1 i v5fb v v5 = 0 v ? 74 ? 92 ? 135 ma thermal protection thermal shutdown threshold t jtsd t j rising 155 170 ? oc thermal shutdown hysteresis t jtsdhys ?20?oc 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. 3 ?20c ensured by design and characterization, not production tested.
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance vreg output versus temperature t on versus temperature v5 output versus temperature v5p output versus temperature 3v3 output versus temperature 1v2 output versus temperature 5.40 5.41 5.42 5.43 5.44 5.45 5.46 5.47 5.48 5.49 5.50 -40 -20 0 20 40 60 80 100 120 140 vreg output voltage (v) temperature (c) 0 100 200 300 400 500 600 700 800 900 1,000 1,100 1,200 1,300 1,400 -40 -20 0 20 40 60 80 100 120 140 t on pulse width (ns) temperature (c) 7.5 13.5 27 35 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 -40 -20 0 20 40 60 80 100 120 140 v5 output voltage (v) temperature (c) 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 -40 -20 0 20 40 60 80 100 120 140 v5p output voltage (v) temperature (c) 3.27 3.28 3.29 3.30 3.31 3.32 3.33 -40 -20 0 20 40 60 80 100 120 140 3v3 output voltage (v) temperature (c) 1.190 1.195 1.200 1.205 1.210 1.215 1.220 -40 -20 0 20 40 60 80 100 120 140 1v2 output voltage (v) temperature (c) v in (v)
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com enbat start / stop thresholds versus temperature enable start / stop thresholds versus temperature cpor charging current versus temperature enbats (low) voltage versus temperature vreg valley current limit versus temperature 1v2 a nd 3v3 overcurrent threshold versus temperature 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 -40 -20 0 20 40 60 80 100 120 140 enbat threshold (v) temperature (c) start stop 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40-20 0 20406080100120140 enable threshold (v) temperature (c) start stop 10 11 12 13 14 15 16 -40 -20 0 20 40 60 80 100 120 140 cpor charging current (ua) temperature (c) 0 50 100 150 200 250 300 350 400 -40 -20 0 20 40 60 80 100 120 140 npor voltage at 4 ma (mv) temperature (c) 250 275 300 325 350 375 400 425 450 -40 -20 0 20 40 60 80 100 120 140 vreg valley current limit (mv) temperature (c) 180 190 200 210 220 230 240 250 260 270 -40 -20 0 20 40 60 80 100 120 140 overcurrent threshold (mv) temperature (c) 1v2 3v3
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description overview the A4407 contains a constant on-time (cot), buck switch- ing pre-regulator with valley sensing current mode control, two integrated 5 v linear regulators, and two n-channel fet drivers: one for a 1.2 v, 1.5 v, or 1.8 v linear regulator, and the other for a 3.3 v linear regulator. the cot converter maintains a constant output frequency because the on-time is inversely proportional to the supply voltage. as the input voltage decreases, the on-time is increased, which maintains a relatively constant period and frequency. valley mode current control allows the converter to achieve very short on-times because current is measured during the off-time, so there is no requirement for blanking. with very low input voltages, the buck switch transitions to a 100% duty cycle. this turns the buck switch on 100% of the time (no switching), and allows the regulator to operate in dropout mode. the device is enabled via the logic level input (enb) or the high voltage ignition input (enbat). when the device is enabled, the converter starts up under the control of a 10 ms internal soft start ramp. the two enable inputs are logically ored together, so either of the inputs can be used to enable the device. both inputs must be low to disable the device. under light load conditions, the switch enters pulse-skipping mode to ensure regulation is maintained. in order to accept a wide input voltage range, the switcher period is extended when either the minimum on- or off-time is reached, or when the input supply is at either end of its range. the A4407 features overcurrent protection on all regulators including the vreg pre-regulator. the buck switch current limit is determined by the selection of the sense resistor between the isenx pins. output current from the internal 5 v and 5 v protected linear regulators is also monitored, and if shorted the outputs would fold back. the external fet drivers have current limit sensing that can be used with a sense resistor to trigger fold back protection. buck dropout mode the topology of a cot timer is ideal for systems that have high input voltages. because current is measured during the off-time, very short on-times can be achieved. with low input voltages, the switcher must maintain very short off-times. to prevent the switcher from reaching its minimum off-time, the switcher is designed to enter a 100% duty cycle mode. this causes the switcher to stop acting as a buck switch. the voltage at the vreg pin then becomes simply the supply voltage minus the drop across the buck switch and inductor. in this mode, maximum available current may be lower, depending on ambient tempera- ture and supply voltage while in dropout mode. soft start an internal ramp generator and counter allow the output voltages to ramp up. this limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any dc load at startup. internally, the ramp is set to 10 ms typical. the following conditions are required to trigger a soft start: ? enbat or enb transition high, and ? there is no thermal shutdown (tsd = 0), and ? 3v3 voltage is below its undervoltage lockout (uv) threshold, and ? 1v2 voltage is below its uv threshold, and ? vreg voltage is below its uv threshold buck pulse width (ton) a resistor from the ton input to vin sets the on-time of the converter for a given input voltage. when the supply voltage is between 8.6 and 31 v, the switcher period remains constant, based on the selected value of r ton . at voltages lower than 6.5 v, the switch is in dropout mode (100% duty cycle). within reasonable input voltage ranges, the period of the converter is held constant. this results in a constant operating frequency across the input supply range. more information on how to choose r ton can be found in the application information section. the formula to calculate the on-time resistor value is: t on = ( r ton / v in ) 6.36 10 ?12 + 5 10 ?9 (ns) (1) buck current sense (isen+, isen?) the sense inputs are used to sense the current in the buck regula- tor free-wheeling diode during the off-time. the value of the
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sense resistor, r sense , between the isenx pins, can be calcu- lated from: r sense = v isen / i lim(valley) (2) where v isen is documented in the electrical characteristics table, 350 mv typical, and i lim(valley) is the lowest current measured during the off-time. it is recommended that the current sense resistor be sized so that, at peak output current, the voltage at the isen? pin does not exceed ?0.75 v during pwm operation (that is, a transient condi- tion). because the diode current is measured when the inductor current is at the valley, the average output current is greater than the i lim(valley) value. the value for i lim(valley) should be: i lim(valley) = i out(avg) ? 0.5 i ripple + k (3) where i out(avg) is the average of all the regulator outputs cur- rents, i ripple is the inductor ripple current, and k is a design margin allowing for component tolerances. the peak current in the switch is simply: i peak = i lim(valley) + i ripple (4) information on how to calculate the ripple current is included in the application information section. buck overcurrent protection the converter utilizes pulse-by-pulse valley current limiting, which is activated when the current through the sense resis- tor (that is, the buck output current) is high enough to create ?350 mv at the isen ? pin. during an overload condition, the switch is turned on for a period determined by the constant on-time circuitry. the switch off-time is extended until the cur- rent decays to the current limit value set by the selection of the sense resistor, at which point the switch is allowed to turn-on again. because no slope compensation is required in this control scheme, the current limit is maintained at a reasonably constant level across the input voltage range. figure 1 illustrates how the current is limited during an overload condition. the current decay (period with switch off) is propor- tional to the output voltage. as the overload is increased, the out- put voltage tends to decrease and the switching period increases. lx short circuit protection if the lx node is shorted to ground, there would be a relatively high peak current in the buck mosfet within a very short time. the A4407 protects itself by detecting the unusually high current, turning off the buck mosfet, and latching itself off. to avoid false tripping, the current required to activate the peak current protection, i lim(peak) , 5.5 a typical, is set well above the normal range of currents. after peak current limiting is activated, the A4407 will be latched off until either: v in is cycled below its uvlo threshold, or the A4407 is disabled (both enbat and enb must be brought low) and re-enabled. npor is not directly activated (pulled low) by the peak current protection circuitry. however, npor will be in the correct state depending on the vreg, 3v3, and 1v2 outputs. time current limit level current limit level inductor current inductor current constant on-time constant period extended period maximum load overload time constant on-time figure 1. buck current limiting during overload conditions: (upper) with inductor current operating at maximum load, and (lower) inductor current operating in a ?soft? overload.
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com missing asynchronous diode protection in most high voltage asynchronous buck regulators, if the asyn- chronous diode is missing or damaged the lx pin will transition to a very high negative voltage when the upper mosfet turns off, resulting in damage to the regulator. the A4407 includes protection circuitry to detect when the asynchronous diode is missing or damaged. if the lx pin becomes more negative than 1.2 v for more than 200 ns, the A4407 will latch itself in the off state to prevent damage. after a missing diode fault occurs, the latch must be reset by either cycling vin or enbat or enb. see figure 2 for the missing diode voltage threshold and time filtering versus temperature. thermal shutdown if the A4407 junction temperature becomes too high, a thermal shutdown circuit would disable the vreg output, thus protect- ing the A4407 from damage. when a thermal shutdown occurs, the buck regulator stops switching and the vreg voltage decays. when vreg crosses uvlo threshold for it, the npor signal is pulled low. thermal shutdown is not a latched condition, so when the junction temperature cools to an acceptable level, the A4407 automatically restarts. power on reset (npor) the npor output is an open drain pin that can be used to signal a reset event to a dsp or microcontroller. the npor block actively monitors enbat, enb, 3v3, 1v2, vcp, and vreg. during power-up, npor is held low for a programmable amount of time ( t npor ) after vreg, 3v3, and 1v2 all transition above the upper uvlo threshold for each. the rising edge delay allows time for the regulators to be within specification when the dsp or microcontroller begins processing. the amount of the rising edge delay is determined by the value of the external capacitor from the cpor pin to ground. the rising delay can be calculated from the following equation: t npor = 92.3 10 3 c por (seconds) (5) any of the following conditions forces npor to transition low immediately (within a few microseconds): ? 3v3 voltage falls below its uvlo threshold, or ? 1v2 voltage falls below its uvlo threshold, or ? vreg voltage falls below its uvlo threshold, or ? enbat and enb are both low, or ? charge pump voltage, v cp , is too low, or ? internal ic power rail voltage, v rail , is too low when a thermal shutdown (tsd) occurs: pwm switching termi- nates; vreg, or 3v3, or 1v2 decay below the uvlo threshold for it; and npor transitions low. thus, a tsd event indirectly causes npor to transition low. when the A4407 is disabled (enb and enbat are both low or v in is removed) the npor output is held low until the voltage from the 3.3v regulator (3v3) falls below 1.0 v (see figure 3). this assumes maximum initial current (4 ma) in the npor open drain dmos. the npor voltages would be somewhat lower for lower values of i npor . figure 3. npor and 3v3 shutdown characteristics figure 2. missing diode protection versus device junction temperature enb, enbat v 3v3 i npor v npor 3.3 v 1.0 v 0.3 ma 800 mv 4ma 350 mv typ 400 mv 170 175 180 185 190 195 200 205 210 215 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -50 -25 0 25 50 75 100 125 150 time filtering (ns) nega ve voltage threshold (v) junc on temperature (c) voltage threshold time filtering
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 5 v regulator (v5) the 5v linear regulator is provided to supply local circuitry. this regulator can deliver 310 ma typical, 215 ma minimum. when a direct short is applied to this regulator, the output current folds back to 0 v at approximately 92 ma typical (figure 4). 5 v protected tracking regulator (v5p) the 5vp linear tracking regulator is provided to supply remote circuitry such as off-board sensors. the output is monitored and in case of a short to battery condition the output is disabled and protected until the short is removed. the regulator can deliver 415 ma typical, 280 ma minimum. when a direct short is applied to this regulator, the output the current folds back to 0 v at approximately 110 ma typical (figure 5). the v5p regulator is designed to track the either the 3v3 output or the v5 output. the v5p master reference is set by the status of the track pin. the v5p regulator will track the 3.3v output to within 0.5% and the v5 output to within 25 mv under normal steady state operating conditions. if the master reference (either 3v3 or v5) is decreasing, the v5p regulator will accurately track the master reference down to the point at which the master reference crosses its undervoltage threshold (either v 3v3uv(l) or v 1v2uv(l) in the electrical characteristic tables). 6 5 4 3 2 1 0 50 100 150 200 250 300 350 500 450 400 output voltage (v) output current (ma) typical minimum figure 5. fold back current limiting of the 5vp regulator figure 4. fold back current limiting of the 5 v regulator 6 5 4 3 2 1 0 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 output voltage (v) output current (ma) typical minimum
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figures 6 and 7 show the A4407 operation when the v5p pin is shorted to ground and v in (battery). in both cases, the v5p output is disabled and/or disconnected while the other outputs (vreg, v5, v33, and 1v5) remain active. tracking control the track input sets the master reference for the v5p track- ing regulator. track is meant to be either connected to ground or left unconnected by the pcb routing. when track is left unconnected, it is pulled high by an internal current source and v5p tracks the 3v3 regulator. when track is connected to ground, then v5p tracks the v5 regulator. 3v3 linear regulator (3v3) a 3.3 v linear regulator can be implemented using an external mosfet. in the event the 3.3 v regulator output is shorted to ground, the A4407 protects the external mosfet by folding back when the programmed current limit, i 3v3lim , is exceeded. the current limit is determined by the voltage developed across the external sense resistor, r cl1 , shown in the functional block diagram. the 3.3 v regulator current limit can be calculated using the following formula: i 3v3lim = v cl3v3 / r cl1 (6) where v cl3v3 is documented in the electrical characteristics table, 235 mv typical. usually, r cl1 has a fairly low value so it will not dissipate significant power ( 1 / 4 w should be adequate) but the tolerance should be 1% or less. when i 3v3lim is exceeded, the maximum load current through the external mosfet is folded back to 27% typical of i 3v3lim as shown in figure 8. 3.5 3.0 2.5 2.0 1.5 1.0 05 0 50 10 20 30 40 50 60 120 90 100 110 80 70 output voltage (v) percentage of normal current se ng (%) typical minimum maximum figure 8. fold back current limiting of the 3v3 regulator figure 6. v5p shorted to ground in 5 s (d v5p is populated); shows v reg (ch1, 2 v/div.), v 3v3 (ch2, 1 v/div.), v v5 (ch3, 2 v/div.), v 1v5 (ch4, 1 v/div.), v v5p (ch5, 2 v/div.), t = 10 s/div. t v reg v 3v3 v v5 v 1v5 v v5p c1 c3 c5 c4 c2 figure 7. v5p is shorted to a 25 v battery; shows v vreg (ch1, 2 v/div.), v 3v3 (ch2, 2 v/div.), vin pin (ch3, 5 v/div.), v v5p (ch4, 5 v /div.), t = 10 s/div. t v 3v3 v reg v v5p 5 v 25 v 30 v vin pin ringing due to parasitics from a long wire v5p is clamped to a safe level above vin by d2 (see application schematic) all
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 1.2 v/1.5 v/1.8 v linear regulator (1v2) a 1.2 v, 1.5 v, or 1.8 v linear regulator can be implemented using an external mosfet. in the event this regulator output is shorted to ground, the A4407 protects the external mosfet by folding back when the programmed current limit, i 1v2lim , is exceeded. the current limit is determined by the voltage developed across the external sense resistor, r cl2 , shown in the functional block diagram. the 1.2 v/1.5 v/1.8 v regulator current limit can be calculated using the following formula: i 1v2lim = v cl1v2 / r cl2 (7) where v cl1v2 is documented in the electrical characteristic table, 218 mv typical. usually r cl2 has a fairly low value so it will not dissipate significant power ( 1 / 4 w should be adequate) but the tolerance should be 1% or less. when i 1v2lim is exceeded, the maximum load current through the external mosfet is folded back to 27% typical of i 1v2lim , as shown in figure 9. this regulator is designed to provide 1.2 v, but by using an exter- nal resistive divider between v out1v2 and the 1v2 pin, other voltages can be achieved, such as1.5 v or 1.8 v. charge pump the charge pump is used to generate a supply above v in . a 0.22 f monolithic ceramic capacitor should be connected between vcp and vin to act as a reservoir to run the internal dmos and the external mosfets. the vcp voltage is internally monitored to ensure that the switching regulator would be dis- abled in the case of a fault condition. a 0.22 f ceramic mono- lithic capacitor should be connected between cp1 and cp2. enbat enbat is a level-triggered enable input, used to enable the device based on a high voltage ignition or battery switch (via a 1 k resistor). the enbat comparator thresholds are v ign(l) = 2.2 v minimum and v ign(h) = 4.0 v maximum. enbat is used only as a momentary switch to enable, or wake up, the A4407. the enb and enbat signals are logically ored together inter- nally, so individually either can wake up the A4407, that is, only one of these two inputs must be pulled high in order to enable the A4407. however, when enbat is removed, enb must be high to keep the A4407 enabled. if there is no need for the ignition switch, enbat can be pulled low, making enb a single reset control. power-up and power-down scenarios using these inputs are shown in figures 10 and 11. when an external resistor and capacitor are used to form a low-pass filter to the enbat pin, then a 100 resistor must be used to prevent the external capacitor from discharging into and damaging the enbat pin. see the functional block diagram for connection of these three components. enbats when a logic high is sensed on the enbat input, the enbats open drain output goes high, signaling to the user that the ignition input is high. when a logic low is sensed on the enbat input, then enbats transitions low. the enbats input logic levels are identical to the enbat input logic levels. enb this pin can be used as an enable input from either a dsp or a microcontroller. this input has an internal pull down resistor so it can be left unconnected if not needed. figure 9. fold back current limiting of the 1v2 regulator 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 50 10 20 30 40 50 60 120 90 100 110 80 70 output voltage (v) percentage of normal current se ng (%) typical minimum maximum
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 10. typical power-up and power-down by enbat and enb with v in = 13.5 v; enbats is assumed to be connected to 3v3 via a pull up resistor vin npor cpor enbats enbat enb v5 v5p 3v3 internal v rail or vcp vreg v h =4.0v v l =2.2v 10 ms 20 ms 1. 2 v 13.5 v v h =5.00v v h =2.95 v clamped at 8.5 v via 1 k v l =4.94v v l =2.83v v h =2v v l =0.8v internal uvlo 1.0 v 0. 8 v max internal uvlo 1v2 v h =1.07v v l =1.01 v vreg > 5.00v and 3v3 > 2.95v and 1v2 > 1.07v enb < 0.8v or vreg < 4.94v or 3v3 < 2.83v or 1v2 < 1.01v or vcp low or int. vrail low npor is open-drain, pulled up to 3v3 decay rates of vreg, v5, v5p, 3v3, and 1v2 depend on output capacitances and loading enbats is open-drain, pulled up to 3v3 v5, v5p, 3v3, 1v2 ramp at approximately the same rate as vreg
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vin npor cpor enbats enbat enb v5 v5p 3v3 internal v rail or vcp vreg 10 ms 20 ms 1. 2 v 13.5 v v h =5.00v v h =2.95v v l =4.94v v l =2.83 v 6.5 v internal uvlo 5.2 v 5.5 v 4. 9 v v enbat = 0v enbats is not connected 100 % duty cycle internal regulators collapse 0.8 v max 1.0 v internal uvlo 1v2 v h =1.07v v l =1.01 v v enb 2v prior to v in ramping up vreg > 5.00v and 3v3 > 2.95v and 1v2 > 1.07v enb < 0.8v or vreg < 4.94v or 3v3 < 2.83v or 1v2 < 1.01v or vcp low or vrail low v5p tracks 3v3 until v 3v3uv(l) or v in < 5.5 v v5, v5p, 3v3, 1v2 ramp at approximately the same rate as vreg npor is open-drain, pulled up to 3v3 decay rates of vreg, v5, v5p, 3v3, and 1v2 depend on output capacitances and loading figure 11. typical power up and power down via vin with enb always logic high; enbat and enbats are not used
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com component selection buck on-time and switching frequency in order for the switcher to maintain regulation, the energy that is transferred to the inductor during the on-time must be transferred to the capacitor during the off-time. because of this relationship, the load current and ir drops, as well as the input and output voltages, affect the on-time of the converter. the equation that governs switcher on-time is: = t on v in + v f ? ( r ds(on) i peak ) t sw [ v reg + ( r l i peak ) + v f + ( r sense i p e (8) the effects of the voltage drop on the inductor and trace resis- tance affect the switching frequency. however, the frequency variation due to these factors is small, and is covered in the varia- tion of the switcher period, which is 25% of the target. remov- ing these current dependant terms simplifies the equation: = t on v in + v f ? ( r ds(on) i peak ) f sw v reg + v f + ( r sense i peak )1 (9) be sure to use worst-case sense voltage and forward voltage of the diode including any effects due to temperature. for the example provided, assume a 1 a converter with a supply voltage of 13.5 v. the output voltage is 5.45 v, v f is 0.45 v, r sense i peak is 0.34 v, r ds(on) i peak is 0.15 v, and the target frequency is 2.2 mhz. applying equation 9, we can solve for t on : = = t on 13.5 (v) + 0.45 (v) ? 0.15 (v) 205 ns 2.2 (mhz) 5.45 (v) + 0.45 (v) + 0.34 (v) 1 the formulas above describe how t on changes based on input and load conditions. because load changes are minimal and the out- put voltage is fixed, the only factor that affects the on-time is the input voltage. the converter is able to maintain a constant period over a varying supply voltage because the on-time changes based on the input voltage. the current into the ton pin is derived from a resistor tied to vin, which sets the on-time proportional to the supply voltage. selecting the resistor value based on the t on calculated above is done using the following formula: = r ton v in ( t on ? 5 (ns) ) 6.36 10 ?12 (10) when the resistor is selected and a suitable t on is found, t on must be demonstrated that it does not, under worst-case conditions, exceed the minimum on-time or minimum off-time of the con- verter. the minimum on-time occurs at maximum input voltage and minimum load. the maximum off-time occurs at minimum supply voltage and maximum load. for supply voltages above 6.5 v but below 8.6 v, refer to the section entitled low voltage operation. low voltage operation the converter can run at very low input voltages; for example, with a 5.25 v output, the minimum input supply can be as low as 5.5 v. when operating at high frequencies, the on-time of the converter must be very short because the available period is short. at high input voltages the converter should not violate the mini- mum on-time, t on(min) , and at low input voltages the converter should not violate the minimum off-time, t off(min) . rather than limit the supply voltage range, the converter solves this problem by automatically increasing the period. with the period extended, the converter does not violate the minimum on-time or off-time specifications. if the input voltage is between 8.6 and 31 v, the converter will maintain a constant period. when calculating worst case on- and off-times, make sure to use the highest switching frequency if the supply voltage is in that range. when operating at voltages below 8.6 v, additional care must be taken when selecting the inductor and diode. at low voltages the maximum current may be limited, due to the ir drops in the current path. when selecting external components for low voltage operation, the ir drops must be considered when determining on-time, so the complete formula (equation 8) should be used to make sure the converter does not violate the timing specification. inductor selection choosing the proper inductor is critical to the correct operation of the switcher. the converter is capable of running at frequencies above 2 mhz, making it possible to use small inductor values and reducing cost and board area. the inductor value determines the ripple current. it is important to size the inductor so that under worst-case conditions the over- current threshold equals the average current minus half the ripple current plus reasonable margin. when the ripple current is too large, the converter reaches current limit. typically, peak-to-peak ripple current should be limited to 20% to 25% of the maximum average load current. application information
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com worst-case ripple current occurs at maximum supply voltage. after calculating the duty cycle for this condition, the ripple cur- rent can be calculated: = d v in (max) + v f ? ( r ds(on) i peak ) v reg + v f + ( r sense i peak ) (11) using the duty cycle, the inductor value can be calculated using the formula below: = ld i ripple v in ? f sw (min) v reg 1 (12) where i ripple is 25% of the maximum load current, and f sw (min) is the minimum switching frequency, nominal frequency minus 25%. continuing the example used above (using equation 9), a 1 a converter with a supply voltage of 13.5 v is the design objec- tive. assume the supply voltage can vary by 10%, the output voltage is 5.45 v, v f is 0.5 v, v sense is 0.20, and the target fre- quency is 2.2 mhz. using equation 11, the duty cycle is calcu- lated to be 36.45%. assume the worst-case frequency is 2.2 mhz minus 20%, or 1.76 mhz. using these numbers in equation 12 shows that the minimum inductance for this converter is 9.6 h. output capacitor the buck converter is designed to operate with a low-esr ceramic output capacitor. when choosing a ceramic capacitor, make sure the rated voltage is at least 3 times the maximum output voltage of the converter. this is because the capacitance of a ceramic decreases the closer it is operated to its rated voltage. it is recommended that the output be decoupled with a 10 f, 16 v, x7r ceramic capacitor. larger capacitance may be required on the outputs if load surges dramatically influence the output volt- age. output voltage ripple is determined by the output capacitance; and the effects of esr and esl can be ignored, assuming recom- mended layout techniques are followed. the output voltage ripple is approximated by: v ripple = i ripple / (8 f sw c out ) (13) input capacitor the value of the input capacitance affects the amount of cur- rent ripple on the input. this current ripple is usually the source of supply-side emi. the amount of interference depends on the impedance from the input capacitor and the bulk capacitance located on the supply bus. in addition to the two 4.7 f capaci- tors, placing a small 0.1 f ceramic capacitor very close to the input supply pin helps reduce emi effects. the small capacitor helps reduce the very high frequency transient currents on the supply line. non-synchronous diode the non-synchronous diode (d buck in the functional block dia- gram) conducts the current during the off-time. a schottky diode is required to minimize the forward drop and switching losses. in order to size the diode correctly, it is necessary to find the aver- age diode conduction current using the following formula: i d(avg) = i load (1 ? d( min )) (14) where d(min) is the minimum duty cycle, defined as: d( min ) = (v reg + v f ) / (v in + v f ) (15) where v in is the maximum input voltage and v f is the maximum forward voltage of the diode. the average power dissipation in the diode is: p d buck(avg) = i buck(avg) d( min ) v f (16) the power dissipation in the sense resistor must also be consid- ered using i 2 r and the minimum duty cycle. external mosfet selections to choose an external mosfet for the 3.3 v or for the 1.2 v/1.5 v/1.8 v linear regulator, consider: the maximum drain- to-source voltage, v ds , the maximum continuous drain current, i d , the threshold voltage, v gsth , the on-resistance (r ds(on)(fet) ), and the thermal resistance (r jc(fet) ).
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the buck switcher pre-regulates the voltage to the external mosfet, so even under worst-case conditions, it does not have to support more than 7 v from drain to source. also, the external ldos usually deliver 500 ma to 1 a. numerous mosfets are available, with v ds ratings of at least 20 v, that can support much more than 1a. these two goals should not be difficult to achieve. the A4407 gate drive circuitry is guaranteed to pull the g3v3 and g1v2 voltage down to 1 v, maximum. therefore, allegro recommends using external mosfets with a v gs threshold higher than 1 v. do not use a mosfet that will conduct signifi- cant current when v gs is at 1 v and the system is at the highest expected ambient temperature. one of the more critical specifications is the mosfet on- resistance, r ds(on)(fet) . if the on-resistance were too high, then the external regulator would not be able to maintain its output at the maximum load current. calculate the typical r ds(on)(fet) (at 25c) using the following formula: 2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 12 shows recommended values of r drop1 versus the mosfet thermal resistance at various 3.3 v regulator maxi- mum current settings, i 3v3lim . this graph assumes: steady-state operation (that is, for t >> 50 ms), a pcb temperature of 135c, a maximum mosfet junction temperature of 175c, a duty cycle for t on of 100% , a v bat of 6.69 v, and an output of 3.23 v from the 3.3 v linear regulator. this graph takes into account the volt- age drop across the 3.3 v current limit resistor, r cl1 . after a value for r drop1 is determined, the designer should calculate its maximum power dissipation (i 2 r) and select an appropriate component, allowing adequate design margin. assuming the r drop1 value was chosen from figure 12, then figure 13 shows the power dissipated by r drop1 versus the mosfet thermal resistance at various 3.3 v regulator current settings. the exact value of r drop1 is not critical, so a component with 1% or 5% tolerance could be used. 1.2 v/1.5 v/1.8 v regulator external resistors (r cl2 , r drop2 ) in the functional block diagram, there are two resistors, r cl2 and r drop2 from the output of the 3.3 v regulator to the drain of the 1.2 v/1.5 v/1.8 v external mosfet. r cl2 must always be present because it sets the 1.2 v/1.5 v/1.8 v regulator current limit threshold. however, r drop2 , if used, prevents the external mosfet from dissipating too much power. the value of r drop2 depends on the maximum pcb temperature, the maximum current load on the 1.2 v/1.5 v/1.8 v regulator (i 1v2lim ), the maximum allowable junction temperature of the mosfet, and the thermal resistance of the mosfet. as the thermal resistance of the mosfet decreases, the required value of r drop2 also decreases. if the mosfet is relatively large and has a very low thermal resistance, then r drop2 is not required (0 ). figure 12. r drop1 value versus 3.3 v mosfet thermal resistance at various 3.3 v regulator maximum current settings figure 13. r drop1 power dissipation versus 3.3 v mosfet thermal resistance at various 3.3 v regulator maximum current settings 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 15 20 25 30 35 40 45 80 65 60 70 75 55 50 p d(rdrop2) (w) mosfet thermal resistance (c/w) 635 ma 710 ma 785 ma 850 ma 935 ma 3.0 2.8 2.5 2.3 2.0 1.8 1.5 1.3 1.0 0.8 0.5 0.3 0 15 20 25 30 35 40 45 80 65 60 70 75 55 50 r drop1 ( ) mosfet thermal resistance (c/w) 635 ma 710 ma 785 ma 850 ma 935 ma
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 14 shows recommended values of r drop2 versus mosfet thermal resistance at various 1.5 v regulator maximum current settings, i 1v2lim . this graph assumes a pcb temperature of 135c, a maximum mosfet junction temperature of 175c, and 3.37 v from the upstream (3.3 v) linear regulator. this graph takes into account the voltage drop across the 1.5 v current limit resistor, r cl2 . after a value of r drop2 is determined the designer should calcu- late its maximum power dissipation (i 2 r) and select an appro- priate component, allowing adequate design margin. assuming the r drop2 value was chosen from figure 14, then figure 15 shows the power dissipated by r drop2 versus the mosfet ther- mal resistance at various 1.5 v regulator current settings. the exact value of r drop2 is not critical, so a component with 1% or 5% tolerance could be used. 2.0 1.8 1.5 1.3 1.0 0.8 0.5 0.3 0 30 35 40 45 80 85 90 95 100 65 60 70 75 55 50 r drop2 ( ) mosfet thermal resistance (c/w) 675 ma 600 ma 525 ma 450 ma 375 ma 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 p d(rdrop2) (w) mosfet thermal resistance (c/w) 30 35 40 45 80 85 90 95 100 65 60 70 75 55 50 675 ma 600 ma 525 ma 450 ma 375 ma figure 14. r drop2 value versus 1.5 v mosfet thermal resistance at various 1.5 v regulator maximum current settings figure 15. r drop2 power dissipation versus 1.5 v mosfet thermal resistance at various 1.5 v regulator maximum current settings
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pcb component placement and routing the board layout has a large impact on the performance of the device. it is important to isolate high current ground returns to minimize ground bounce that could produce reference errors in the device. the method used to isolate power ground from noise sensitive circuitry is to use a star ground. this approach makes sure that the high current components such as the input capacitor, output capacitor, and diode have very low impedance paths to each other. figure 16 illustrates the technique. the ground traces for each of the components should be very close to each other and should be connected to each other on the same surface as the components. internal ground planes should not be used for the star ground connection, because vias add impedance to the current path. in order to further reduce noise effects on the pcb, noise sensi- tive traces should not be connected to internal ground planes. the feedback network from the switcher output should have an independent ground trace that goes directly to the exposed pad underneath the device. the exposed pad should be connected to internal ground planes and to any exposed copper used for heat dissipation. if the grounds from the device are also connected directly to the exposed pad, the ground reference from the feed- back network will be less susceptible to noise injection or ground bounce. to reduce radiated emissions from the high frequency switching nodes, it is important to have an internal ground plane directly under the lx node. that ground plane should not be broken directly under the node, because the lowest impedance path back to the star ground is directly under the signal trace. if another trace does break the return path, the energy would have to find another path, which would be through radiated emissions. the peak-to-peak amplitude of the buck current sense signal will typically be only tens of millivolts. the current sense pins, isen+ and isen?, and internal differential amplifier comprise a differential signal receiver, and balanced pair of traces should be routed from the pins of the buck current sense resistor, r sense , as shown in figure 17 (upper panel). the isen+ pin and the sense resistor ground should not be separated by simply using local via connections to the ground plane (figure 17 lower panel). incorrect routing of the isen+ pin would likely add an offset error to the buck current sense signal. star ground lx q1 A4407 d buck current path (off-cycle) current path (on-cycle) r sense l1 vin c in r load c out1 figure 16. illustration of star ground connection figure 17. comparison of routing paths for the traces between the A4407 isen+ and isen? traces and the sense resistor, r sense lx isen ? isen + A4407 differential amplifier d buck (asynchronous) r sense l1 + ? lx isen ? isen + ground plane A4407 differential amplifier d buck (asynchronous) r sense l1 + ? correct routing of isen+ and isen? traces (direct on same plane) incorrect routing of isen+ and isen? traces (using vias to a ground plane)
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application circuit performance application schematic is shown in functional block diagram. b uc k r egu l a t or b o d e pl o t s at i load = 215 ma and 1.1 a 60 65 70 75 80 85 90 95 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 e ? ciency (%) output current, i out (a) -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 drop (%) output current, i out (a) -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.000 0.100 0.200 0.300 0.400 0.500 v out percentage v out percentage drop (%) output current, i out (a) b uc k r egu l a t or (vreg) effi c i ency buck regulator (vreg) load regulation linear regulator load regulation v in = 8 v v in = 12 v v in = 16 v v in = 8 v v in = 12 v v in = 16 v v5 v5p 3v3 1v5 frequency (khz) phase () gain (db) 10 3 100 10 1 10 ?1 60 48 36 24 12 0 -12 -24 -36 -48 -60 200 160 120 80 40 0 -40 -80 -120 -160 -200 gain 215 ma gain 1.1 a gain margin 15 db phase 215 ma phase margin 215 ma (46) phase margin 1.1 a (51) phase 1.1 a gain 0 db ( 65 khz) bill of materials for critical components this design is capable of full load, 135c ambient, and 5.5 v bat indefinitely with an adequate thermal solution component description package manufacturer part number q 3v3 mosfet, 40 v, 90 a, 4.3 m , t j 175c dpak infineon ipd90n04s3-04 q 1v5 mosfet, 30 v, 30 a, 13.5 , t j 175c dpak infineon ipd135n03lg r sense , r cl1 resistor, 0.300 , 1 / 4 w, 1% 1206 r cl2 resistor, 0.390 , 1 / 4 w, 1% 1206 r drop1 resistor, 2.2 total, 2 w total, 5% multiple smt components may be used in parallel or series r drop2 resistor, 1.5 , 1 w, 5% 2512 vishay/dale crcw25121r50jneg c in1 , c in2 capacitor, ceramic, 4.7 f, 50 v, 10%, x7r 1210 murata gcm32er71h475ka55l c out1 capacitor, ceramic, 10 f, 16 v, 10%, x7r 1206 kemet c1206c106k4ractu c out2 capacitor, ceramic, 0.47 f, 16 v, 10%, x7r 0603 c out3v3 , c out1v5 , c outv5 , c outv5p capacitor, ceramic, 2.2 f, 16 v, 10%, x7r 1206 murata grm31mr71c225ka35l d buck , d in diode, schottky, 2 a, 40 v sma diodes, inc. b240a-13-f l1 inductor, 10 h, 64 m , 2.39 a sat , 165c 7.6 x 7.6 mm cooper/bussman dra73-100-r
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com startup at v bat = 13.5 v; shows v reg (ch1, 2 v/div.), v 3v3 (ch2, 2 v/div.), v 1v5 (ch3, 1 v/div.), npor (ch4, 2 v /div.), t = 5 ms/div. t v 3v3 v 1v5 npor v reg c1 c3 c4 c2 pwm at v bat = 12 v with a 25 ma load; shows v reg (ch1, 5 v/div.), v lx (ch2, 5 v/div.), i l (ch3, 100 ma/div.), t = 2 s/div. t v reg v lx i l c1 c3 c2 pwm at v bat = 12 v with a 1.0 a load; shows v reg (ch1, 5 v/div.), v lx (ch2, 5 v/div.), i l (ch3, 100 ma/div.), t = 200 ns/div. t v reg v lx i l c1 c3 c2 startup at v bat = 13.5 v; shows v reg (ch1, 2 v/div.), v v5 (ch2, 2 v/div.), v v5p (ch3, 2 v/div.), npor (ch4, 2 v /div.), t = 5 ms/div. c1 c3 c4 c2 t v v5 v v5p npor v reg startup at v bat = 6.5 v; shows v reg (ch1, 2 v/div.), v v5 (ch2, 2 v/div.), v v5p (ch3, 2 v/div.), npor (ch4, 2 v /div.), t = 5 ms/div. c1 c3 c4 c2 t v v5 v v5p npor v reg startup at v bat = 6.5 v; shows v reg (ch1, 2 v/div.), v 3v3 (ch2, 2 v/div.), v 1v5 (ch3, 1 v/div.), npor (ch4, 2 v /div.), t = 5 ms/div. t v 3v3 v 1v5 npor v reg c1 c3 c4 c2
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com t v 3.3v i 3.3v c1 c2 v 3.3v transient response, 125 to 250 ma; shows v 3.3v (ch1, 50 mv/div.), i 3.3v (ch2, 100 ma/div.), t = 50 s/div. t v 1.5v transient response, 225 to 450 ma; shows v 1.5v (ch1, 50 mv/div.), i 1.5v (ch2, 200 ma/div.), t = 50 s/div. v 1.5v i 1.5v c1 c2 t v v5 i v5 c1 c2 v v5 transient response, 100 to 200 ma; shows v v5 (ch1, 50 mv/div.), i v5 (ch2, 100 ma/div.), t = 50 s/div. t v reg i l c1 c2 v reg short circuit operation at v in = 12 v; shows v reg (ch1, 2 v/div.), i l (ch2, 500 ma/div.), t = 5 s/div. t v v5p transient response, 125 to 250 ma; shows v v5p (ch1, 50 mv/div.), i v5p (ch2, 100 ma/div.), t = 50 s/div. v v5p i v5p c1 c2 t v reg normal (left) and overload (right) operation at v in = 12 v; shows v reg (ch1, 2 v/div.), i l (ch2, 250 ma/div.) v reg v reg normal operation (before overcurrent event) overloaded operation (during overcurrent condition) i l i l c1 c2
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 28 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 24-pin tssop with exposed thermal pad a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 24x 0.65 bsc 0.25 bsc 2 1 24 7.800.10 4.400.10 6.400.20 gauge plane seating plane a terminal #1 mark area b for reference only; not for tooling use (reference mo-153 adt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b exposed thermal pad (bottom surface) 4.32 nom 3 nom 0.65 6.10 3.00 4.32 1.65 0.45 reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view c c
2.2 mhz constant on-time buck regulator with two external and two internal linear regulators A4407 29 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 2 november 19, 2012 change in schematics, application information

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